The session covers the fundamentals of CNNs and their implementation in RTL for FPGA-based AI acceleration. Participants will explore camera-based real-time digit recognition (0–9), CNN hardware architecture, parallel processing, pipelining, and optimized inference on the Xilinx ZedBoard. The session demonstrates how custom RTL-based CNN designs can deliver low-latency, high-performance inference while providing practical insights into FPGA-based AI development for academic labs, research, and embedded vision applications.